View HD49334AHNP_4234653.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HD49334ANP/AHNP
CDS/PGA & 10-bit A/D Converter
REJ03F0106-0200 Rev.2.00 May 20, 2005
Description
The HD49334ANP/AHNP is a CMOS IC that provides CDS-PGA analog processing (CDS/PGA) suitable for CCD camera digital signal processing systems together with a 10-bit A/D converter in a single chip.
Functions
* * * * * * * Correlated double sampling PGA Offset compensation Serial interface control 10-bit ADC Operates using only the 3 V voltage Corresponds to switching mode of power dissipation and operating frequency Power dissipation: 120 mW (Typ), maximum frequency: 36 MHz (HD49334AHNP) Power dissipation: 60 mW (Typ), maximum frequency: 25 MHz (HD49334ANP) * ADC direct input mode * QFN 36-pin package
Features
* Suppresses low-frequency noise output from CCD by the S/H type correlated double sampling. * The S/H response frequency characteristics for the reference level can be adjusted using values of external parts and registers. * High sensitivity is achieved due to the high S/N ratio and a wide coverage provided by a PG amplifier. * Feedback is used to compensate and reduce the DC offsets including the output DC offset due to PGA gain change and the CCD offset in the CDS (correlated double sampling) amplifier input. * PGA, standby mode, etc., is achieved via a serial interface. * High precision is provided by a 10-bit-resolution A/D converter.
Rev.2.00 May 20, 2005 page 1 of 21
HD49334ANP/AHNP
Pin Arrangement
ADCIN AVSS AVDD BIAS BLKC CDSIN BLKFB BLKSH AVDD
VRM VRT VRB DVDD DVSS CS SDATA SCK D0
27 26 25 24 23 22 21 20 19 28 18 17 29 30 16 31 15 14 32 33 13 34 12 11 35 36 10 123456789
D1 D2 D3 D4 D5 D6 D7 D8 D9
AVSS SPSIG SPBLK OBP PBLK DVDD ADCLK DVSS DRDVDD
(Top view)
Pin Description
Pin No. 1 to 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Symbol D0 to D9 DRDVDD DVSS ADCLK DVDD PBLK OBP SPBLK SPSIG AVSS AVDD BLKSH BLKFB CDSIN BLKC BIAS AVDD AVSS ADCIN VRM VRT VRB Description Digital output Output buffer power supply (3 V) Digital ground (0 V) ADC conversion clock input pin Digital power supply (3 V) Preblanking input pin Optical black pulse input pin Black level sampling clock input pin Signal level sampling clock input pin Analog ground (0 V) Analog power supply (3 V) Black level S/H pin Black level FB pin CDS input pin Black level C pin Internal bias pin Connect a 33 k resistor between BIAS and AVSS. Analog power supply (3 V) Analog ground (0 V) ADC input pin Reference voltage pin 1 Connect a 0.1 F ceramic capacitor between VRM and AVSS. Reference voltage pin 3 Connect a 0.1 F ceramic capacitor between VRT and AVSS. Reference voltage pin 2 Connect a 0.1 F ceramic capacitor between VRB and AVSS. I/O O -- -- I -- I I I I -- -- -- -- I -- -- -- -- -- -- -- -- Analog(A) or Digital(D) D D D D D D D D D A A A A A A A A A A A A A
Rev.2.00 May 20, 2005 page 2 of 21
HD49334ANP/AHNP
Pin Description (cont.)
Pin No. 31 32 33 34 35 36 Note: Symbol DVDD DVSS CS SDATA SCK D0 Description Digital power supply (3 V) Digital ground (0 V) Serial interface control input pin Serial data input pin Serial clock input pin Digital output I/O -- -- I I I O Analog(A) or Digital(D) D D D D D D
1. With pull-down resistor.
Input/Output Equivalent Circuit
Pin Name Digital output D0 to D9
DIN STBY
Equivalent Circuit
DVDD Digital output
Digital input
ADCLK, OBP, SPBLK, SPSIG, CS, SCK, SDATA, PBLK CDSIN
DVDD Digital input
Analog
AVDD CDSIN
Internally connected to VRT
ADCIN
ADCIN
AVDD
Internally connected to VRM
BLKSH, BLKFB, BLKC
BLKFB
AVDD
+ -
BLKSH BLKC
VRT, VRM, VRB
VRT
+ -
+ -
VRM VRB AVDD
+ -
BIAS
BIAS
AVDD
Rev.2.00 May 20, 2005 page 3 of 21
HD49334ANP/AHNP
Block Diagram
DRDVDD ADCLK SPBLK SPSIG DVDD AVDD DVSS AVSS
16 18 19 Timing generator
31 16 18 19 19 42 OEB
ADCIN 27 PBLK 26 CDSIN 26 BLKSH 28 BLKC 28 CDS
9 D9 PGA 10bit ADC 8 D8 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 D1 D0
BLKFB 29
DC offset compensation circuit
Serial interface
Bias generator
17
44 45 43
35
32 34 33
VRT
SDATA
Rev.2.00 May 20, 2005 page 4 of 21
BIAS
VRM
OBP
VRB
SCK
CS
Output latch circuit
HD49334ANP/AHNP
Internal Functions
Functional Description * CDS input CCD low-frequency noise is suppressed by CDS (correlated double sampling). The signal level is clamped at 14 LSB to 76 LSB by resister during the OB period. *1 Gain can be adjusted using 8 bits of register (0.132 dB steps) within the range from -2.36 dB to 31.40 dB. *2 * ADC input The center level of the input signal is clamped at 512 LSB (Typ). Gain can be adjusted using 8 bits of register (0.01784 times steps) within the range from 0.57 times (-4.86 dB) to 5.14 times (14.22 dB). *1 * Automatic offset calibration of PGA and ADC * DC offset compensation feedback for CCD and CDS * Pre-blanking CDS input operation is protected by separating it from the large input signal. Digital output is set at clamp level by resister. * Digital output enable function Notes: 1. It is not covered by warranty when 14LSB settings 2. Full-scale digital output is defined as 0 dB (one time) when 1 V is input. Operating Description Figure 1 shows CDS/PGA + ADC function block.
ADCIN C2 CDSIN C1 SH AMP Gain setting (register) Current DAC BLKC BLKFB C3 BLKSH C4 OBP DAC Clamp data (register) CDS AMP PG AMP 10bit ADC D0 to D9 Offset calibration logic DC offset feedback logic
VRT
Figure 1 HD49334ANP/AHNP Functional Block Diagram 1. CDS (Correlated Double Sampling) Circuit The CDS circuit extracts the voltage differential between the black level and a signal including the black level. The black level is directly sampled at C1 by using the SPBLK pulse, buffered by the SHAMP, then provided to the CDSAMP. The signal level is directly sampled at C2 by using the SPSIG pulse, and provided to CDSAMP (see figure 1). The difference between these two signal levels is extracted by the CDSAMP, which also operates as a programmable gain amplifier at the previous stage. The CDS input is biased with VRT (2 V) during the SPBLK pulse validation period. During the PBLK period, the above sampling and bias operation are paused.
Rev.2.00 May 20, 2005 page 5 of 21
HD49334ANP/AHNP 2. PGA Circuit The PGAMP is the programmable gain amplifier for the latter stage. The PGAMP and the CDSAMP set the gain using 8 bits of register. The equation below shows how the gain changes when register value N is from 0 to 255. In CDSIN mode: Gain = (-2.36 dB + 0.132 dB) x N (LOG linear). In ADCIN mode: Gain = (0.57 times + 0.00446 times) x N (linear). Full-scale digital output is defined as 0 dB (one time) when 1 V is input. 3. Automatic Offset Calibration Function and Black-Level Clamp Data Setting The DAC DC voltage added to the output of the PGAMP is adjusted by automatic offset calibration. The data, which cancels the output offset of the PGAMP and the input offset of the ADC, and the clamp data (14 LSB to 76 LSB) set by register are added and input to the DAC. The automatic offset calibration starts automatically after the RESET mode set by register 1 is cancelled and terminates after 40000 clock cycles (when fclk = 20 MHz, 2 ms). 4. DC Offset Compensation Feedback Function Feedback is done to set the black signal level input during the OB period to the DC standard, and all offsets (including the CCD offset and the CDSAMP offset) are compensated for. The offset from the ADC output is calculated during the OB period, and SHAMP feedback capacitor C3 is charged by the current DAC (see figure 1). The open-loop differential gain (Gain/H) per 1 H of the feedback loop is given by the following equation. 1H is the one cycle of the OBP. Gain/H = 0.078/(fclk x C3) (fclk: ADCLK frequency, C3: SHAMP external feedback capacitor) Example: When fclk = 20 MHz and C3 = 1.0 F, Gain/H = 0.0039 When the PGAMP gain setting is changed, the high-speed lead-in operation state is entered, and the feedback loop gain is increased by a multiple of N. Loop gain multiplication factor N can be selected from 4 times, 8 times, 16 times, or 32 times by changing the register settings (see table 1). Note that the open-loop differential gain (Gain/H) must be one or lower. If it is two or more, oscillation occurs. The time from the termination of high-speed lead-in operation to the return of normal loop gain operation can be selected from 1 H, 2 H, 4 H, or 8 H. If the offset error is over 32 LSB, the high-speed lead-in operation continues, and when the offset error is 32 LSB or less, the operation returns to the normal loop-gain operation after 1 H, 2 H, 4 H, or 8 H depending on the register settings. See table 2.
Table 1 Loop Gain Multiplication Factor during High-Speed Lead-In Operation
HGain-Nsel (register settings) [0] [1] L L H L L H H H Multiplication Factor N 4 8 16 32
Table 2 High-Speed Lead-In Operation Cancellation Time
HGstop-Hsel (register settings) [0] [1] L L H L L H H H Cancellation Time 1H 2H 4H 8H
5. Pre-Blanking Function During the PBLK input period, the CDS input operation is separated and protected from the large input signal. The ADC digital output is fixed to clamp data (14 to 76 LSB).
Rev.2.00 May 20, 2005 page 6 of 21
HD49334ANP/AHNP 6. ADC Digital Output Control Function The ADC digital output includes the functions output enable, code conversion, and test mode. Tables 3, 4 and 5 show the output functions and the codes. Table 3 ADC Digital Output Functions
TEST0 TEST1 PBLK STBY MINV LINV
ADC Digital Output D7 D6 D5 D4
D9
D8
D3
D2
D1
D0
H L
X L
H
Notes: 1. 2. 3.
X X X Hi-Z L L H Same as in table 4. L H H D9 is inverted in table 4. H L H D8 to D0 are inverted in table 4. H H H D9 to D0 are inverted in table 4. X X L Output code is set up to Clamp Level. H L L H Same as in table 5. L H H D9 is inverted in table 5. H L H D8 to D0 are inverted in table 5. H H H D9 to D0 are inverted in table 5. X X L Output code is set up to Clamp Level. H L H L H L X L L X L L H L H L L H X H H L H L H H L X L H L H L H H H X STBY, TEST, LINV, and MINV are set by register. Mode setting for the PBLK is done by external input pins. The polarity of the PBLK pin when the register setting is SPinv is low. X L
Operating Mode Low-power wait state Normal operation
Pre-blanking Normal operation
H H L L
L L H H
H H L L
L L H H
Pre-blanking Test mode
Table 4
ADC Output Code
3 4 5 6 511 512 1020 1021 1022 1023 D9 L L L L L H H H H H D8 L L L L H L H H H H D7 L L L L H L H H H H D6 L L L L H L H H H H D5 L L L L H L H H H H D4 L L L L H L H H H H D3 L L L L H L H H H H D2 L H H H H L H H H H D1 H L L H H L L L H H D0 H L H L H L L H L H
Output Pin Output Steps codes
Table 5
ADC Output Code (TEST1)
3 4 5 6 511 512 1020 1021 1022 1023 D9 L L L L L H H H H H D8 L L L L H H L L L L D7 L L L L L L L L L L D6 L L L L L L L L L L D5 L L L L L L L L L L D4 L L L L L L L L L L D3 L L L L L L L L L L D2 L H H H L L L L L L D1 H H H L L L H H L L D0 L L H H L L L H H L
Output Pin Output Steps codes
Rev.2.00 May 20, 2005 page 7 of 21
HD49334ANP/AHNP 7. Adjustment of Black-Level S/H Response Frequency Characteristics The CR time constant that is used for sampling/hold (S/H) at the black level can be adjusted by changing the register settings, as shown in table 6. Table 6 SHSW CR Time Constant Setting
SHSW-fsel (Register setting) [0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3] LLLLHLLLLHLLHHLLLLHLHLHLLHHLHHHL 2.20 nsec 2.30 nsec 2.51 nsec 2.64 nsec 2.93 nsec 3.11 nsec 3.52 nsec 3.77 nsec CR Time Constant (Typ) (cutoff frequency conversion) (72 MHz) (69 MHz) (63 MHz) (60 MHz) (54 MHz) (51 MHz) (45 MHz) (42 MHz) SHSW-fsel (Register setting) [0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3] LLLHHLLHLHLHHHLHLLHHHLHHLHHHHHHH 4.40 nsec 4.80 nsec 5.87 nsec 6.60 nsec 8.80 nsec 10.6 nsec 17.6 nsec 26.4 nsec CR Time Constant (Typ) (cutoff frequency conversion) (36 MHz) (33 MHz) (27 MHz) (24 MHz) (18 MHz) (15 MHz) (9 MHz) (6 MHz)
8. The SHAMP frequency characteristics can be adjusted by changing the register settings and the C4 value of the external 23rd pin. The settings are shown in table 7. Values other than those shown in the table 7 cannot be used.
Table 7 SHAMP Frequency Characteristics Setting
[0] H [1] L SHA-fsel (Register setting) [0] [1] L H 75 MHz 13000 pF (300 pF) 32 MHz 22000 pF (750 pF)
BLKC 23 C4
116 MHz 10000 pF (270 pF) 49 MHz "Hi" 15000 pF (620 pF) Note: Upper line : SHAMP cutoff frequency (Typ) Middle line : Standard value of C4 (maximum value is not defined) Lower line : Minimum value of C4 (do not set below this value)
LoPwr (Register setting) "Lo"
[0] H 56 MHz 18000 pF (360 pF) 24 MHz 27000 pF (820 pF)
[1] H
Rev.2.00 May 20, 2005 page 8 of 21
HD49334ANP/AHNP
Timing Chart
Figure 2 shows the timing chart when CDSIN and ADCIN input modes are used.
0 1 2 ~ 9 10 11
* When CDSIN input mode is used
N N+1 N+2 N+9 N+10 N+11
CDSIN
SPBLK
SPSIG
ADCLK
D0 to D9
N-10
N-9
N-8
N-1
N
* When ADCIN input mode is used
N ADCIN N+1 N+2 N+8 N+9 N+10 N+11
ADCLK
D0 to D9
N-9
N-8
N-1
N
N+1
Note: The phases of SPBLK and SPSIG are those when the serial data SPinv bit is set to low.
Figure 2 Output Timing Chart when CDSIN and ADCIN Input Modes are Used * The ADC output (D0 to D9) is output at the rising edge of the ADCLK in both modes. * Pipe-line delay is ten clock cycles when CDSIN is used and nine when ADCIN is used. * In ADCIN input mode, the input signal is sampled at the rising edge of the ADCLK.
Rev.2.00 May 20, 2005 page 9 of 21
HD49334ANP/AHNP
Detailed Timing Specifications
Detailed Timing Specifications when CDSIN Input Mode is Used Figure 3 shows the detailed timing specifications when the CDSIN input mode is used, and table 8 shows each timing specification.
Black level
CDSIN
(2) (1) (5) (4) (3)
Signal level
SPBLK
Vth
SPSIG
(7)
(6) (8) (9) (10)
Vth Vth
ADCLK
D0 to D9
Note: 1. When serial data Spinv bit is set to low. (When the Spinv bit is set to high, the polarities of the SPBLK and the SPSIG are inverted.)
Figure 3 Detailed Timing Chart when CDSIN Input Mode is Used Table 8
No. (1) (2) (3) (4) (5) (6) (7), (8) (9) (10) Note:
Timing Specifications when the CDSIN Input Mode is Used
Timing Black-level signal fetch time 1 SPBLK low period * Signal-level fetch time 1 SPSIG low period * SPBLK rising to SPSIG rising time * 1 SPBLK rising to ADCLK rising inhibition time * ADCLK tWH min./tWL min. ADCLK rising to digital output hold time ADCLK rising to digital output delay time
1
Symbol tCDS1 tCDS2 tCDS3 tCDS4 tCDS5 tCDS6 tCDS7, 8 tCHLD9 tCOD10
Min -- Typ x 0.8 -- Typ x 0.8 Typ x 0.85 1 11 3 --
Typ (1.5) 1/4fCLK (1.5) 1/4fCLK 1/2fCLK 5 -- 7 16
Max -- Typ x 1.2 -- Typ x 1.2 Typ x 1.15 11 -- -- 24
Unit ns ns ns ns ns ns ns ns ns
1. SPBLK and SPSIG polarities when serial data Spinv bit is set to low.
OBP Detailed Timing Specifications Figure 4 shows the OBP detailed timing specifications. The OB period is from the fifth to the twelfth clock cycle after the OB pulse is input. The average of the black signal level is taken for eight input cycles during the OB period and becomes the clamp level (DC standard).
OB period *1
CDSIN OBP
N
N+1
N+5
N+12
N+13
OB pulse > 2 clock cycles
This edge is used, when OBP pulse-width period is clamp-on.
When serial data OBPinv bit is set to low (When the OBPinv is set to high, the polarity of the OBP is inverted.)
Note: 1. Shifts 1 clock cycle depending on the OBP input timing.
Figure 4 OBP Detailed Timing Specifications
Rev.2.00 May 20, 2005 page 10 of 21
HD49334ANP/AHNP Detailed Timing Specifications at Pre-Blanking Figure 5 shows the pre-blanking detailed timing specifications.
PBLK
Vth
VOH Digital output (D0 to D9) ADC data Clamp level ADC data
VOL ADCLK x 10 clocks (shifts one clock cycle depending on the PBLK input timing) When serial data SPinv bit is set to low (When the SPinv is set to high, the PBLK polarity is inverted.) tPBLK ADCLK x 2 clocks
Figure 5 Detailed Timing Specifications at Pre-Blanking Detailed Timing Specifications when ADCIN Input Mode is Used Figure 6 shows the detailed timing chart when ADCIN input mode is used, and table 9 shows each timing specification.
ADCIN
(2) (3) (4) (5)
(1)
ADCLK
Vth
D0 to D9
VDD/2
Figure 6 Detailed Timing Chart when ADCIN Input Mode is Used Table 9
No. (1) (2), (3) (4) (5)
Timing Specifications when ADCIN Input Mode is Used
Timing Signal fetch time ADCLK tWH min./tWL min. ADCLK rising to digital output hold time ADCLK rising to digital output delay time Symbol tADC1 tADC2, 3 tAHLD4 tAOD5 Min -- Typ x 0.85 10 -- Typ (6) 1/2fADCLK 14.5 23.5 Max -- Typ x 1.15 -- 31.5 Unit ns ns ns ns
Rev.2.00 May 20, 2005 page 11 of 21
HD49334ANP/AHNP
Serial Interface Specifications
Table 10 Serial Data Function List
Resister 0 DI 00 (LSB) DI 01 DI 02 DI 03 DI 04 DI 05 DI 06 DI 07 DI 08 DI 09 DI 10 DI 11 DI 12 DI 13 DI 14 Low Low Low Cannot be used. All low PGA gain setting (LSB) PGA gain setting PGA gain setting PGA gain setting PGA gain setting PGA gain setting PGA gain setting PGA gain setting (MSB) Cannot be used. All low Resister 1 High Low Low Resister 2 Low High Low C-Bias off Output mode setting (TEST1) Cannot be used. All low 0 0 0 0 0 1 0 0 1 Cannot be used. Cannot be used. Resister 3 High High Low Resister 4 to 7 *7 Test Mode (can not be used) Low to High Low to High High
SLP Low: Normal operation mode Clamp-level [0] (LSB) High: Sleep mode STBY Low: Normal operation mode Clamp-level [1] High: Standby mode Output mode setting (LINV) Output mode setting (MINV) Clamp-level [2] Clamp-level [3]
Output mode setting (TEST0) Clamp-level [4] (MSB) SHA-fsel [0] (LSB) SHA-fsel [1] (MSB) SHSW-fsel [0] (LSB) SHAMP High-speed frequency HGstop-Hsel [0] lead-in charactercancellation istics HGstop-Hsel [1] time switching
HGain-Nsel [0] High-speed lead-in SHSW gain SHSW-fsel [1] frequency HGain-Nsel [1] multiplication characteristics SHSW-fsel [2] Low_PWR switching SPinv, SHSW-fsel [3] (MSB) SPSIG/SPBLK/PBLK inversion Cannot be used. All low OBPinv, OBP inversion RESET Low: Reset mode High: Normal operation mode
DI 15 (MSB) CSEL Low: CDSIN input mode High: CIN input mode
CS
Latches SDATA at SCK rising edge tINT1 fSCK
Data is determined at CS rising edge tINT2
SCK tsu SDATA tho DI DI DI DI DI DI DI DI DI DI DI DI DI DI DI DI 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15
Figure 7 Serial Interface Timing Specifications
Notes: 1. 2. 3. 4. 5. 6. 2 byte continuous communications. SDATA is latched at SCK rising edge. Insert 16 clocks of SCK while CS is low. Data is invalid if data transmission is aborted during transmission. The gain conversion table differs in the CDSIN input mode and the ADCIN input mode. STBY: Reference voltage generator circuit is in the operating state. SLP: All circuits are in the sleep state. 7. This bit is used for the IC testing, and cannot be used by the user. The use of this address is prohibited. 8. Circuit current and the frequency characteristic are switched. Data = 0: 36 MHz guarantee Data = 1: 25 MHz guarantee
Timing Specifications Min Max fSCK 5 MHz tINT1, 2 50 ns tsu 50 ns 50 ns tho
Rev.2.00 May 20, 2005 page 12 of 21
HD49334ANP/AHNP Explanation of Serial Data of CDS Part Serial data of CDS part has the following functions. * PGA gain (D5 to D12 of register 0) Details are referred to page 5 block diagram. At CDS_in mode: -2.36 dB + 0.132 dB x N (Log linear) At ADC_in mode: 0.57 times + 0.01784 times x N (Times linear) : Full-scale digital output is defined as 0 dB when 1 V is input. Above PGA gain definition means input signal 1 Vp-p to CDS_in, and set N = 18 (correspond 2.36 dB), and then PGA outputs the 2 V full-range, and also ADC out puts the full code (1023). This mean offset gain of PGA has 6 dB - 2.36 dB = 3.64 dB, therefore it should be decided that how much dB add on.
(1.0 V) (2.0 V) (1023)
(1.0 V) CDS PGA ADC
0 dB when set N = 18 which correspond to 2.36 dB (1) Level dia explain 2V 1023
CDS
PGA
ADC
(CDS = 0 dB) 3.64 dB + 0.132 dB x N (2) Level dia on the circuit
Figure 8 Level Dia of PGA * CSEL (D15 of register 0) Data = 0: Select CDSIN Data = 1: Select ADCIN
1 1 1 Address 1 0 0 0 1 STD1[7:0] (L) STD2[15:8] (H) D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8
LINV
STBY
MINV
test0
SLP
test_I2
SHSW_fsel
SHA_fsel
* SLP and STBY (D3, D4 of register 1) SLP: Stop the all circuit. Consumption current of CDS part is less than 10 A. Start up from offset calibration when recover is needed. STBY: Only the standard voltage generating circuit is operated. Consumption current of CDS part is about 3 mA. Allow 50 H time for feedback clamp is stabilized until recover. * Output mode (D5 to D7 of register 1 and D4 of register 3) It is a test mode. Combination details are table 3 to 5. Normally set to all 0. * SHA-fsel (D8 to D9 of register 1) It is a LPF switching of SH amplifier. Frequency characteristics are referred to page 9. To get rough idea, set the double cut off frequency point with using. * SHSW-fsel (D10 to D13 of register 1) It is a time constant which sampling the black level of SH amplifier. Frequency characteristics are referred to page 9. To get rough idea, set the double cut off frequency point with using. S/N changes by this data, so find the appropriate point with set data to up/down.
Rev.2.00 May 20, 2005 page 13 of 21
HD49334ANP/AHNP * Clamp (D3 to D7 of register 2) Determine the OB part level with digital code of ADC output. Clamp level = setting data x 2 + 14 Default data is 9 = 32 LSB. * HGstop-Hsel, HGain-Nsel (D8 to D11 of register 2) Determine the lead-in speed of OB clamp. Details are referred to page 7. PGA gain need to be changed for switch the high speed leading mode. Transfer the gain +1/-1 to previous field, its switch to high speed leading mode. * Low_PWR (D12 of register 2) Switch circuit current and frequency characteristic. Data = 0: 36 MHz guarantee Data = 1: 25 MHz guarantee * SPinv (D13 of register 2) SPSIG/SPBLK/PBLK input signal inverted switching. Data = 1: Normal Data = 0: Inverted * Reset (D15 of register 2) Software reset. Data = 1: Normal Data = 0: Reset Offset calibration should be done when starting up with using this bit. Details are referred to page 18. * C_Bias_off (D3 of register 3) Center bias is turned off in ADCIN mode. Data = 0: Normally on Data = 1: Off * Ave_4H (D6 of register 3) Clamp detection data is averaged 4H. Data = 0: 1H Data = 1: Averaged 4H Differential Code and Gray Code (D4 to D5 and D7 to D9 of register 3) * Gray code (D4 to D5 of register 3) DC output code can be change to following type.
Gray Code [1] 0 0 1 1 Gray Code [0] 0 1 0 1 Output Code Binary code Gray code Differential encoded binary Differential encoded gray
* Serial data setting items (D7 to D9 of register 3)
Setting Bit Gray_test[0] Gray_test[1] Gray_test[2] Setting Contents Standard data output timing control signal (Refer to the following table) ADCLK polar with OBP. (LoPositive edge, HINegative edge)
* Standard data output timing
Gray_test[1] Low Low High High Gray_test[0] Low High Low High Standard Data Output Timing Third and fourth Fourth and fifth Fifth and sixth Sixth and seventh
Rev.2.00 May 20, 2005 page 14 of 21
HD49334ANP/AHNP Ripple (pseudo outline made by quantized error) occurres on the point which swithing the ADC output multiple bit in parallel. When switching the several of ADC output at the same time, ripple (pseudo outline caused by miss quantization) occurs to the image. Differential code and gray code are recommended for this countermeasure. Figure 9 indicates circuit block. When luminance signal changes are smoothly, the number of bit of switching digital output bit can be reduced and easily to reduce the ripple using this function. This function is especially effective for longer the settings of sensor more than clk = 30 kHz, and ADC output. Figure 10 indicates the timing specifications.
10 ADC 2clk_DL Standard data control signal (D9,D8,D7) Differential SW(D5) + - Carry bit round Standard data selector Gray SW(D4) GrayBinary conversion 10-bit output
Figure 9 Differential Code, Gray Code Circuit
(In case of select the positive edge of ADCLK with D8)
ADCLK OBP
(In case of select the positive polar) (Beginning edge of OBP and standard edge of ADCLK should be exept 5 ns) 1 2 3 4 5 6 7 8 9 10 11
Digital output Differential data
Standard data
Differential data
Figure 10 Differential Code Timing Specifications To use differential code, complex circuit is necessary at DSP side.
Carry bit round Standard data selector 2clk_DL D9 D8 D7 D9 D8 D7
From ADC
Gray Binary
Standard data control signal
D0
D0
(1) Differential coded
(2) Gray Binary conversion
Figure 11 Complex Circuit Example
Rev.2.00 May 20, 2005 page 15 of 21
HD49334ANP/AHNP
Absolute Maximum Ratings
(Ta = 25C) Item Power supply voltage Analog input voltage Digital input voltage Operating temperature Power dissipation Storage temperature Power supply voltage range Symbol VDD(max) VIN(max) VI(max) Topr Pt(max) Tstg Vopr Ratings 4.1 -0.3 to AVDD +0.3 -0.3 to DVDD +0.3 -10 to +75 400 -55 to +125 2.7 to 3.3 Unit V V V C mW C V
Notes: 1. VDD indicates AVDD and DVDD. 2. AVDD and DVDD must be commonly connected outside the IC. When they are separated by a noise filter, the potential difference must be 0.3 V or less at power on, and 0.1 V or less during operation.
Electrical Characteristics
(Unless othewide specified, Ta = 25C, AVDD = 3.0 V, DVDD = 3.0 V, and RBIAS = 33 k)
* Items Common to CDSIN and ADCIN Input Modes
Item Power supply voltage range Conversion frequency Digital input voltage Symbol VDD fCLK hi fCLK low VIH VIL VIH2 VIL2 Digital output voltage Digital input current VOH VOL IIH IIH2 IIL Digital output current ADC resolution ADC integral linearity ADC differential linearity+ ADC differential linearity- Sleep current IOZH IOZL RES INL DNL+ DNL- ISLP Min 2.7 20 5.5
DVDD 2.0 x 3.0
Typ 3.0 -- -- -- -- -- -- -- -- -- -- -- -- -- 10 3 0.3 -0.3 0
Max 3.3 36 25 DVDD
DVDD 0.8 x 3.0
Unit V MHz MHz V V V V V V A A A A A bit LSBp-p LSB LSB A
Test Conditions
Remarks
LoPwr = low LoPwr = high
HD49334AHNP HD49334ANP Digital input pins other than CS, SCK and SDATA CS, SCK, SDATA
0
DVDD 2.25 x 3.0
DVDD
DVDD 0.6 x 3.0
0 DVDD -0.5 -- -- -- -50 -- -50 10 -- -- -0.9 -100
-- 0.5 50 250 -- 50 -- 10 -- 0.9 -- 100
IOH = -1 mA IOL = +1 mA VIH = 3.0 V VIH = 3.0 V VIL = 0 V VOH = VDD VOL = 0 V fCLK = 25 MHz fCLK = 25 MHz fCLK = 25 MHz Digital input pin is set to 0 V, output pin is open Digital I/O pin is set to 0 V *1 *1
Standby current
ISTBY
--
3
5
mA
Notes: 1. Differential linearity is the calculated difference in linearity errors between adjacent codes. 2. Values within parentheses ( ) are for reference.
Rev.2.00 May 20, 2005 page 16 of 21
HD49334ANP/AHNP
Electrical Characteristics (cont.)
(Unless othewide specified, Ta = 25C, AVDD = 3.0 V, DVDD = 3.0 V, and RBIAS = 33 k)
* Items for CDSIN Input Mode
Item Consumption current (1) Consumption current (2) CCD offset tolerance range Timing specifications (1) Timing specifications (2) Timing specifications (3) Timing specifications (4) Timing specifications (5) Timing specifications (6) Timing specifications (7) Timing specifications (8) Timing specifications (9) Timing specifications (10) Clamp level Symbol IDD1 IDD2 VCCD tCDS1 tCDS2 tCDS3 tCDS4 tCDS5 tCDS6 tCDS7 tCDS8 tCHLD9 tCOD10 CLP(00) CLP(09) CLP(31) PGA gain at CDS input PGA(0) PGA(63) PGA(127) PGA(191) PGA(255) Min -- -- (-100) -- Typ x 0.8 -- Typ x 0.8 Typ x 0.85 1 11 11 3 -- -- -- -- -4.4 4.1 12.5 21.0 29.4 Typ 45.0 23.5 -- (1.5) 1/4fCLK (1.5) 1/4fCLK 1/2fCLK 5 -- -- 7 16 (14) (32) (76) -2.4 6.1 14.5 23.0 31.4 Max 54.5 31.0 (100) -- Typ x 1.2 -- Typ x 1.2 Typ x 1.15 9 -- -- -- 24 -- -- -- -0.4 8.1 16.5 25.0 33.4 Unit mA mA mV ns ns ns ns ns ns ns ns ns ns LSB LSB LSB dB dB dB dB dB CL = 10 pF See table 8 Test Conditions fCLK = 36 MHz fCLK = 25 MHz Remarks CDSIN mode LoPwr = low CDSIN mode LoPwr = high
Note : Values within parentheses ( ) are for reference.
* Items for ADCIN Input Mode
Item Consumption current (3) Consumption current (4) Timing specifications (11) Timing specifications (12) Timing specifications (13) Timing specifications (14) Timing specifications (15) Input current at ADC input Clamp level at ADC input PGA gain at ADC input Symbol IDD3 IDD4 tADC1 tADC2 tADC3 tAHLD4 tAOD5 IINCIN OF2 GSL(0) GSL(63) GSL(127) GSL(191) GSL(255) Min -- -- -- Typ x 0.85 Typ x 0.85 10 -- -110 -- 0.45 1.36 2.27 3.18 4.08 Typ 30.0 17.0 (6) 1/2fADCLK 1/2fADCLK 14.5 23.5 -- (512) 0.57 1.71 2.86 4.00 5.14 Max 38.0 21.5 -- Typ x 1.15 Typ x 1.15 -- 31.5 110 -- 0.72 2.16 3.60 5.04 6.47 Unit mA mA ns ns ns ns ns A LSB Times Times Times Times Times VIN = 1.0 V to 2.0 V CL = 10 pF Test Conditions fCLK = 36 MHz fCLK = 25 MHz Remarks ADCIN mode LoPwr = low ADCIN mode LoPwr = high See table 9
Note : Values within parentheses ( ) are for reference.
Rev.2.00 May 20, 2005 page 17 of 21
HD49334ANP/AHNP
Operation Sequence at Power On
Must be stable within the operating power supply voltage range VDD SPBLK Start control SPSIG of TG and ADCLK camera DSP OBP etc. 0 ms or more HD49334ANP/AHNP serial data transfer 0 ms or more
2 ms or more
0 ms or more (2) Register 2 setting (3) Registers 0, 1 and 3 settings
(1) Register 2 setting 2 ms or more
RESET bit
RESET = "Low" (RESET mode)
RESET = "High" (RESET cancellation)
Automatic offset calibration
Offset calibration (automatically starts after RESET cancellation) Ends after 40000 clock cycles
The following describes the above serial data transfer. For details on registers 0, 1, 2, and 3, refer to table 10. (1) Register 2 setting (2) Register 2 setting : Set all bits in register 2 to the usage condition, and set the RESET bit to low. : Cancel the RESET mode by setting the register 2 RESET bit to high. Do not change other register 2 settings. Offset calibration starts automatically. (3) Register 0, 1 and 3 settings : After the offset calibration is terminated, set registers 0, 1 and 3.
Rev.2.00 May 20, 2005 page 18 of 21
HD49334ANP/AHNP
Notice for Use
1. Careful handling is necessary to prevent damage due to static electricity. 2. This product has been developed for consumer applications, and should not be used in non-consumer applications. 3. As this IC is sensitive to power line noise, the ground impedance should be kept as small as possible. Also, to prevent latchup, a ceramic capacitor of 0.1 F or more and an electrolytic capacitor of 10 F or more should be inserted between the ground and power supply. 4. Common connection of AVDD and DVDD should be made off-chip. If AVDD and DVDD are isolated by a noise filter, the phase difference should be 0.3 V or less at power-on and 0.1 V or less during operation. 5. If a noise filter is necessary, make a common connection after passage through the filter, as shown in the figure below.
Analog +3.0V AVDD AVSS Noise filter DVDD DVSS Digital +3.0V DVDD DVSS Noise filter AVDD AVSS 0.01 F Example of noise filter 100 H 0.01 F
HD49334ANP/AHNP
HD49334ANP/AHNP
6. Connect AVSS and DVSS off-chip using a common ground. If there are separate analog system and digital system set grounds, connect to the analog system. 7. When VDD is specified in the data sheet, this indicates AVDD and DVDD. 8. No Connection (NC) pins are not connected inside the IC, but it is recommended that they be connected to power supply or ground pins or left open to prevent crosstalk in adjacent analog pins. 9. To ensure low thermal resistance of the package, a Cu-type lead material is used. As this material is less tolerant of bending than Fe-type lead material, careful handling is necessary. 10. The infrared reflow soldering method should be used to mount the chip. Note that general heating methods such as solder dipping cannot be used. 11. Serial communication should not be performed during the effective video period, since this will result in degraded picture quality. Also, use of dedicated ports is recommended for the SCK and SDATA signals used in the HD49330AF. If ports are to be shared with another IC, picture quality should first be thoroughly checked. 12. At power-on, automatic adjustment of the offset voltage generated from PGA, ADC, etc., must be implemented in accordance with the power-on operating sequence (see page 15).
Rev.2.00 May 20, 2005 page 19 of 21
HD49334ANP/AHNP
Example of Recommended External Circuit
* At CDS Input R10 R11 R12 R13 R14 C11 0.1 C10 0.1 18 17 16 15 14 13 12 11 10 100 100 100 100 100 from Timing generator
from CCD out C14 0.1 C1 2 1 C3* 1 C4*1 R15 33 k C15 0.1
AVSS SPSIG SPBLK OBP PBLK DVDD ADCLK DVSS DRDVDD
19 AVDD 20 BLKSH 21 BLKFB 22 CDSIN 23 BLKC 24 BIAS 25 AVDD 26 AVSS 27 ADCIN
HD49334ANP/AHNP (CDS/PGA+ADC)
D9 D8 D7 D6 D5 D4 D3 D2 D1
9 8 7 6 5 4 3 2 1 to Camera signal processor
VRM VRT VRB DVDD DVSS CS SDATA SCK D0
28 29 30 31 32 33 34 35 36 C16 47/6 L1 47 3.0 V C17 C18 C19 C22 0.1 0.1 0.1 0.1 Serial data input C21 47/6
L2 47
GND
Notes: 1. For C4, see table 5. 2. For C3, see page 8 "DC Offset Compensation Feedback Function". * At ADC Input C11 0.1 C10 0.1 18 17 16 15 14 13 12 11 10 from Timing generator
AVSS SPSIG SPBLK OBP PBLK DVDD ADCLK DVSS DRDVDD
C14 0.1
19 AVDD 20 BLKSH 21 BLKFB 22 CDSIN 23 BLKC
HD49334ANP/AHNP (CDS/PGA+ADC)
R15 33 k C15 0.1
+ -
24 BIAS 25 AVDD 26 AVSS 27 ADCIN
with ADC input C2 2.2/16
D9 D8 D7 D6 D5 D4 D3 D2 D1
9 8 7 6 5 4 3 2 1 to Camera signal processor
VRM VRT VRB DVDD DVSS CS SDATA SCK D0
28 29 30 31 32 33 34 35 36 C16 47/6 L1 47 3.0 V Note: External circuit is same as above except for ADC input. C17 C18 C19 C22 0.1 0.1 0.1 0.1 Serial data input C21 47/6
L2 47
GND Unit: R: C: F
Rev.2.00 May 20, 2005 page 20 of 21
HD49334ANP/AHNP
Package Dimensions
JEITA Package Code P-VQFN36-6x6-0.50 RENESAS Code PVQN0036KA-A Previous Code TNP-36/TNP-36V MASS[Typ.] 0.07g
HD D 27 19
28
18
HE
E
e
Reference Symbol
Dimension in Millimeters Min Nom 6.0 6.0 0.89 0.95 0.005 0.17 0.02 0.22 0.20 0.5 0.04 0.27 Max
D E 36 10 A2
ZE
A
Lp
A1 b
1 x4 t
9 ZD b b1
xM
b e L
1
p
0.50
0.60
0.70 0.05 0.05
y1
x y
c c1
A2
A
y t
1
0.20 0.20 6.2 6.2 1.0 1.0 0.17 0.22 0.20 0.25
y
A1
HD HE ZD ZE c c
1
Rev.2.00 May 20, 2005 page 21 of 21
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001
http://www.renesas.com
(c) 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon 2.0

▲Up To Search▲

Price & Availability of HD49334AHNP

	To Download HD49334AHNP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .